FPGA implementation of UDP/IP stack using TSE IP core and transfer data at 1 Gbps

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dc.contributor.authorJain, D.
dc.contributor.authorShrivastava, S.
dc.date.accessioned2020-03-19T10:15:37Z
dc.date.available2020-03-19T10:15:37Z
dc.date.issued2017
dc.description.divisionBARCen
dc.format.extent4281 bytes
dc.format.mimetypetext/html
dc.identifier.sourceAdvances in Intelligent Systems and Computing, 2017. Vol. 479: pp. 1103-1111en
dc.identifier.urihttp://hdl.handle.net/123456789/20481
dc.language.isoenen
dc.subjectTSE IP coreen
dc.subjectUDP/IP stacken
dc.subjectAltera Quartus IIen
dc.subjectQsysen
dc.subjectSignal Tap II analyzeren
dc.subjectSystem consoleen
dc.subjectFPGAen
dc.titleFPGA implementation of UDP/IP stack using TSE IP core and transfer data at 1 Gbpsen
dc.typeArticleen

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