High-speed VHDL interfaces are used for transmission of huge amount of data. This paper deals with the development of VHDL code for interfacing with high-speed serial data link: Triple-Speed Ethernet (TSE) IP core. It includes the use of high bandwidth structure, Qsys system as System On Programmable Chip (SOPC) builder system for connecting components. Qsys interconnects the components either available in library or the customized components developed by user with VHDL or Verilog code (using Avalon interface interconnect). Modelsim simulator is used to simulate the developed code, and generated Qsys structure is verified and tested with TCL script in system console. Signal Tap II analyzer is used to analyze the behavior of signals used internally in the design. Data packets are generated using data packet module from the processed data and transmitted over communication channel in order to attain the high-speed data transmission. Transfer of these data packets to data archiving server on Ethernet over open core UDP/IP stack at 1 Gbps data rate.