FPGA implementation of UDP/IP stack using TSE IP core and transfer data at 1 Gbps

No Thumbnail Available

Click here to download

1208.htm (4.18 KB)

Date

2017

Authors

Journal Title

Journal ISSN

Volume Title

Publisher

Abstract

Description

Keywords

TSE IP core, UDP/IP stack, Altera Quartus II, Qsys, Signal Tap II analyzer, System console, FPGA

Source

Advances in Intelligent Systems and Computing, 2017. Vol. 479: pp. 1103-1111

URI

http://hdl.handle.net/123456789/20481

Collections

2017