Qualification of Hardware Description Language Designs for Safety Critical Applications in Nuclear Power Plants

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Date

2020

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Keywords

Bounded model checking, formal verification, field-programmable gate-array (FPGA) qualification, VHDL

Source

IEEE Transactions on Nuclear Science, 2020. Vol. 67 (3): pp. 502-507

URI

http://hdl.handle.net/123456789/22018

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2020